Solid state memory, such as flash memory, may be rendered unusable due to cell degradation, which may be caused by excessive program and erase (P/E) cycles. To help remedy this, wear-leveling algorithms have been implemented to evenly spread the location of the P/E cycles throughout the memory array. However, many solid state memories still suffer from a short usable life due to cell degradation even when they use wear-leveling. Thus, a new system and method of low wear operation is needed.